
module SlotCounter(
  input  wire        clk,
  input  wire        rst_n,
  input  wire        clken,

  output wire [4:0]  slot,
  output wire [1:0]  stage
);

reg[6:0] counter;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	    counter <= #1 7'b0;
    else if(!clken)
	    counter <= #1 counter;
    else if(counter == 7'd71)
	    counter <= #1 7'b0;
    else
	    counter <= counter + 1'b1;
end

assign slot  = counter[6:2];
assign stage = counter[1:0];

endmodule
